Job Title: Senior ASIC Design Engineer CDC/RDC
Location : San Jose, CA 95134 (Hybrid)
Type: Contract
Job Details:
- Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
- Design & implement robust and reusable RTL with CDC/RDC considerations
- Spec comprehensive CDC/RDC check flows and work with CAD team to implement
- Review and approve CDC/RDC constraints and waivers
- Perform static glitch analysis Improve design with prevention of static glitch harzad
Responsibilities:
- Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design
- RTL development skills and experiences
- Solid understanding on CDC/RDC concepts and relevant design implementation
- Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
- Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists
Preferred Qualifications
- Experiences on Static Timing Analysis
- Experiences on VCS simulation SVA (SystemVerilog Assertions)
- Minimum 10 years of experience