Key skills
PerlPythonMentoringCommunication
About this role
Role Overview
- Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
- Developing System Verilog/UVM based communication protocol components,
- Working on test plan based on functional requirements as well as applicable standards requirements
- Working with experts of different areas to ensure the most competitive solutions
- Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues
- Supporting HW/SW bring-up and debug
Requirements
- Masters degree desired, Bachelor's degree in CS/EE is required.
- 8+ years of relevant experience in ASIC verification field.
- Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
- Fluent in System Verilog and scripting languages such as Python or Perl.
- Must have intimate knowledge of UVM methodology.
- Knowledgeable about assertions and functional coverage
- Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
- Very good communication skills and ability and desire to work in a geographically diverse team environment.
- Familiarity with embedded processor & bus functional protocols would be bonus
- Familiarity with external memory interface protocols would be a bonus
- Familiarity with validation experience with any emulation platforms would be a bonus
Tech Stack
- Perl
- Python
Benefits
- Continuous learning opportunities
- Well-being programs to support you mentally and physically
- Opportunities to join and get supported by employee resource groups
- Mentoring programs
- Highly diverse teams with an inclusive culture where people thrive and are empowered