Key skills
PerlPython
About this role
Role Overview
- Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner
- Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them
- Own front-end design quality checks and reviews to present the physical design team with high-quality RTL
Requirements
- A Masters in Computer or Electrical Engineering or equivalent experience
- 5+ years of experience in chip design, specializing in SOC integration and design automation
- Excellent analytical and problem-solving skills
- Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation
- Strong coding skills in Perl, Python, or other industry-standard scripting languages
- Experience in synthesis and physical design is a plus
- Good interpersonal skills.
Tech Stack
- Perl
- Python
Benefits
- Competitive salaries
- Generous benefits package