Key skills
AIML
About this role
Role Overview
- Develop innovative memory subsystem architectures for HBM-based AI/ML solutions
- Define Memory and RAS architecture requirements and drive end‑to‑end architectural specification for next‑generation memory subsystems
- Collaborate with internal and external partners to develop novel architectures and detailed IP requirements
- Lead engagement with IP vendors for evaluation and selection of interface IP and functional IP blocks
- Analyze benchmarks, workloads, and simulation results to identify opportunities in memory subsystems
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- Minimum of 10 years of experience in memory subsystem architecture and design
- Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
- Experience with PHY design and understanding of signal integrity issues
- Proficiency in Network-on-Chip (NoC) architecture and design
- Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, HIF, etc
Benefits
- Medical, dental and vision plans
- Paid family leave
- Robust paid time-off program
- Paid holidays
- Income protection programs