Memory Debug Engineer
United States
Full Time
5 days ago
$141,910 - $269,100 USD
H1B Sponsor
About this role
Role Overview
- Drive the enablement, validation, and complex debugging of memory subsystems
- Provide strategic oversight of memory IO interfaces
- Define and execute the overarching validation and debug strategy for memory IO interfaces
- Lead the reproduction and root-cause analysis of high-priority customer-submitted failure sightings
- Ensure all customer memory IO interfaces meet industry-standard electrical signal integrity (SI) compliance
- Define Memory Reference Code (MRC) requirements for validation and margin optimization
- Act as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and the customer
- Manage and drive task force environments to resolve critical bugs
- Communicate effectively with cross-functional teams and external customers
Requirements
- BS/MS/PhD in Electrical Engineering or Computer Engineering
- 4+ years of industry experience
- 3+ years of experience of DDR4/DDR5, LPDDR4/5 protocols
- 3+ years of experience of debug tools: high-speed oscilloscopes, logic analyzers, margining tools, profilers (e.g. Intel Vtune etc) and protocol exercisers
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- Competitive pay
- Stock bonuses
- Benefit programs which include health
- Retirement
- Vacation