Responsible for ASIC design verification for various processing blocks within a SOC, with a strong focus on cache coherency protocols and complex memory hierarchies.
Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments.
Design and implement constrained-random and directed System Verilog testbenches targeting multi-level cache hierarchies and interconnect fabric.
Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
Drive the development of silicon and platform verification strategies and methodologies.

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
8+ years of experience in ASIC verification, particularly in cache coherency or memory subsystem verification.
Strong knowledge of System Verilog and UVM methodology.
Hands-on experience with AMBA protocols, especially AXI, ACE, and CHI, demonstrating a strong background with AMBA protocols such as AXI, CHI, ATB, etc.
Familiarity with SoC architectures, memory models, and CPU-cache interactions.
Proficiency in scripting languages (Python, Perl, TCL) and working knowledge of C/C++ for testbench or model integration.

Custom SOC IP Verification Engineer

Key skills