Will be a key member of a small FPGA team that will own prototyping of Kandou’s architectures in FPGA
Will need to work independently with low day-to-day supervision and own FPGA projects
Will work with Kandou’s architecture and system software teams on FPGA prototyping and participate in the entire lifecycle of project including support.
Will participate in technical discussions with IP providers and be responsible for driving some of them.

Demonstrated RTL development skills of 5+ years, only 1 can be academic
Proficiency in Verilog and C programming is expected.
Proficiency in using Linux for lab testing is expected.
Working exposure for SystemC and scripting (Python) is desired.
Clear understanding and usage of AXI and related AMBA protocols to connect multiple logical blocks in an FPGA
Demonstrated computer architecture understanding in at least one of processors, PCIe, ethernet or storage protocols
Must have shipping FPGA design in at least one of the following: compute accelerators, networking, storage, processor prototyping
Must have micro-architected, designed & shipped at least two key logic functions of high or medium complexity in an FPGA design
Must have participated in lab bring up & validation of shipping FPGAs in the lab and in deployed use
Must be familiar with Xilinx development tool chain and Versal, Virtex FPGAs
Deep exposure to PCIe devices – protocol design & lab work preferred
Deep exposure to data path blocks (PCIe, Networking or storage) that involved embedded processors in the FPGA preferred.

FPGA Design Engineer

Key skills