Shape the development and deployment of physical design CAD flows and methodologies.
Lead a team of engineers focusing on physical implementation methodology innovation.
Drive automation and scalable infrastructure across concurrent programs.
Provide technical leadership and hands-on support to project teams.
Champion automation and infrastructure development, building robust scripting and tool integrations.
Advance cross-functional collaboration with internal design and DTCO teams.
Inspire high performance by mentoring junior engineers and fostering a culture of ownership and innovation-driven execution.
Requirements
11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
11+ years of hands-on experience in Physical Design CAD, methodology development, or design enablement for complex GPU, CPU, or SoC programs.
Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.
Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.
Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.
Proficiency in scripting and automation (Python, Tcl, shell) with experience building scalable CAD infrastructure.
Experience with leading complex technical initiatives, driving process and methodology innovation, and mentoring engineers.
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence in a fast-paced, global environment.