About this role

Develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM
Create and maintain verification plans focusing on functional and code coverage metrics
Perform black box testing for complex designs
Debug verification issues and provide effective solutions
Collaborate with design teams to align verification strategies with project requirements
Create and maintain detailed documentation for verification processes

Bachelor's or Master's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, or related field
0-2 years of relevant experience in digital design verification
Proficiency in developing and maintaining verification environments using SystemVerilog and UVM
Ability to develop comprehensive test benches for mixed-signal product verification
Capability to create and implement automation scripts using Python, Perl, or TCL
Strong understanding of Register Transfer Level design concepts
Experience with electronic design automation tools

Design Verification Engineer

Key skills