Physical Design Engineer, PNR, Physical Verification, STA, EMIR

Role Overview

• Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes.
• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Requirements

• Bachelor or above degree in majors of EE/CS/IT, with 5+ years work experience
• Extensive knowledge of the design rule for the process of N7/N5 and below
• Knowledge of scripting languages and use in methodology
• Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.
• Deep experience of static timing analysis
• Ability to learn quickly
• High level of communication and teamwork
• Carefulness, responsibility, and persistence

Benefits

• We welcome applications from candidates with disabilities and in equity seeking groups.
• If you have accessibility needs during the application and interview process, we encourage you to make your needs known.
• Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization.
• Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.