Define and engineer high-speed networking and communication systems for AI Inference infrastructure
Develop architectures for chip-to-chip interconnects and switched fabrics tailored for AI/ML scale-out
Analyze trade-offs in bandwidth, latency, power, area, and reliability
Participate in industry standard bodies and contribute/influence/shape the direction of industry specifications
Work with SoC, package design, and software teams to ensure seamless integration

Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
10
15 years experience developing interconnect technologies including transport and link level protocols, switching fabrics, QoS and reliable communication methods, and Software Defined Networking
Familiarity with various fabric topologies such as Fat tree, Leaf-Spine (Clos), Torus, Meshed and their applicability to various workload and system configurations
Familiarity with GPU/accelerator clusters and data center infrastructure
Deep, working knowledge of various interconnect technologies and protocols such as PCIe, CXL, NVLink, UALink, Ethernet, Ultra-Ethernet, and serial links
Ability to develop performance models

Paid vacation time
Paid sick leave
Medical/dental/vision insurance
Life, accident and disability insurance
Tax-advantaged flexible spending and health savings accounts
Employee assistance program
Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
Tuition reimbursement
Transit
The Applause Program
Employee stock purchase plan
Sandisk's Savings 401(k) Plan

Senior Principal AI Interconnect Architect

Key skills