About this role

Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
Constraint generation, timing analysis and optimization.
Execute clock tree synthesis (CTS) and custom clock-building techniques.
Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
Develop automation scripts in Python, Tcl, Bash and contribute to flow development.
Debug and solve technical challenges related to physical design.
Collaborate with architecture, RTL, and verification teams.

10+ years of experience in Physical Design (RTL to GDS)
Strong communication and teamwork skills
Expertise in all aspects of physical design
Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre)
Proficiency in clocking techniques and CTS
Experience in IP integration across various domains
Strong scripting skills (Python and Tcl)
Proven problem-solving and debugging capabilities
Fluent in English (spoken and written)

Senior/Staff Silicon Physical Design Engineer

Key skills