Process Engineer – Die to Wafer Hybrid Bonding, Silicon Photonics / CPO, R&D
Santa Clara, California, United States of America
Full Time
2 weeks ago
$147,000 - $202,500 USD
Visa Sponsor
Key skills
RStatistical AnalysisCommunication
About this role
Role Overview
design and optimize manufacturing processes for display and semiconductor manufacturing technologies
collect and analyze data, perform hardware characterization, and troubleshoot engineering issues
measure film properties, generate technical documentation, and engage with customers to resolve concerns
collaborate with vendors and suppliers
experiment and learn on state‑of‑the‑art equipment along with R&D teams
Requirements
M.S. or Ph.D. in Materials Science, Electrical Engineering, Mechanical Engineering, Applied Physics, or a related STEM discipline
In‑depth knowledge and hands‑on experience in one or more of the following: Die‑to‑wafer or wafer‑to‑wafer bonding, Thin‑die handling and alignment‑critical processes, Semiconductor processing and 2.5D/3D integration
Strong understanding of: Bond interface physics, Alignment and overlay fundamentals, Mechanical behavior of thin and fragile dies
Proficiency in statistical analysis and process control (e.g., DOE, SPC, JMP)
Self‑starter with strong problem‑solving skills; able to work both independently and collaboratively
Strong communication and interpersonal skills, with the ability to collaborate effectively across multidisciplinary teams.
Benefits
supportive work culture that encourages learning, development, and career growth
programs and support for health and wellbeing
opportunities for personal and professional growth