Lead the end-to-end hardware development lifecycle for complex, high-performance AI accelerator PCIe cards and chassis platforms.
Own schematic capture, component selection, and rigorous BOM management for multi-rail, high-power designs.
Architect and oversee the layout of ultra-high-speed interfaces, including PCIe Gen5/6, CXL, and custom chiplet-to-chiplet interconnects.
Design robust power delivery networks capable of handling high-current transients and low-voltage rails characteristic of advanced AI silicon.
Partner closely with Silicon, Signal Integrity (SI/PI), Thermal, and Mechanical teams to ensure seamless integration and performance.
Drive Design for Excellence (DFM, DFT, DFA) to ensure high-yield production and long-term reliability in data center environments.
Act as a technical lead, guiding junior engineers and setting the standard for hardware design best practices across the company.

BS/MS in Electrical Engineering or related field.
10+ years of experience in high-complexity hardware design, specifically within the semiconductor, server, or networking industries.
Mastery of Cadence Allegro/Orcad or similar high-end EDA tools.
Deep understanding of SI/PI fundamentals, including jitter, crosstalk, and impedance control for 32Gbps+ signals.
Proficiency with high-speed oscilloscopes, BERTs, and VNA/TDR for hardware bring-up and validation.
Ability to distill complex technical trade-offs into actionable decisions for executive leadership.

Principal Systems Hardware Engineer

Key skills