Lead Solutions Engineer – Runset Enablement, Physical Verification

Role Overview

• Lead development and validation of Pegasus DRC and LVS runsets for advanced nodes
• Architect automation frameworks for regression execution, issue detection, and validation reporting
• Collaborate with R&D to resolve CCRs, influence product roadmap, and implement performance improvements
• Provide technical enablement and support for customers on tool usage and advanced methodologies
• Mentor junior engineers and establish best practices for runset development and QA
• Work closely with internal teams to ensure timely delivery of verification solutions

Requirements

• MS degree with 5+ years of experience or PhD with 3+ years in Electrical Engineering, Computer Science, or related field
• Strong understanding of semiconductor design and physical verification flows
• Proven expertise in developing and validating DRC and LVS runsets for Pegasus or similar tools (Calibre, ICV, Assura)
• Good-to-have: Experience with PERC and Fill runsets
• Deep knowledge of advanced process technologies and methodologies (Ground Rules, SmartFill, ESD)
• Proficiency in scripting languages (TCL, Python, Perl) and Linux/Unix environments
• Familiarity with chip fabrication processes and multi-die integration challenges
• Experience in automation frameworks for regression and validation

Tech Stack

• Linux
• Perl
• Python
• Unix

Benefits

• Equal employment opportunity and employment equity
• Attract a qualified and diverse candidate pool
• Diversity and inclusion in the workplace