Lead the design and development of next-generation Data Center Storage products, including enterprise-class NVMe Solid State Drive (SSD) controllers and other PCIe-based products.
Own key ASIC/SoC design areas through all phases of development, from architecture definition and microarchitecture to RTL implementation, integration, and silicon bring-up support.
Develop detailed microarchitectural specifications for complex subsystems and drive high-quality RTL implementation in SystemVerilog.
Design and integrate blocks involving industry-standard protocols such as PCIe, ONFI/Toggle NAND, AMBA AXI, and DDR4/5.
Collaborate closely with architecture, verification, emulation, firmware, validation, and physical design teams to ensure robust feature execution and first-silicon success.
Debug and root-cause design issues across simulation, emulation, FPGA, and silicon environments.
Drive design quality with focus on performance, power, area, timing, testability, and scalability.
Support pre-silicon and post-silicon activities to ensure features meet architectural and product requirements.
Evaluate and provide recommendations for architecture choices, third-party IP, design methodologies, and vendor solutions.
Stay current on the latest SoC and storage trends and incorporate relevant innovations into design methodologies and product development.
Provide technical leadership and mentorship to junior engineers across design activities.
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field; Master’s degree preferred.
12+ years of relevant industry experience in ASIC/SoC design, computer system design, or related semiconductor development.
Strong experience in PCIe-based Enterprise Flash Controller design.
Experience with PCIe, DDR, and ONFI/Toggle NAND is highly desired.
Proven ability to develop detailed microarchitectural specifications and translate them into production-quality RTL.
Strong hands-on experience with SystemVerilog-based RTL development.
Experience with all aspects of the SoC/ASIC design flow, including design, verification collaboration, integration, synthesis, timing/power-aware design, and post-silicon support.
Proven track record of successful delivery of silicon IPs and SoCs to production.
Strong debugging and problem-solving skills across RTL, subsystem, and SoC-level issues.
Excellent verbal and written communication skills, with the ability to drive technical discussions across cross-functional teams.
Strong teamwork, planning, and execution skills, with the ability to set direction and thrive in a fast-paced environment.
Participation in relevant standards bodies and ability to represent Microchip in industry forums is a plus.
Tech Stack
Flash
Benefits
health benefits that begin day one
retirement savings plans
industry leading ESPP program with a 2 year look back feature