Support other design team members with Front end tools such as Synthesis, LEC, STA, CDC, RDC and other EDA tools
Participate in the micro-architecture definition of various SubSystems and/or the chip
Write specifications and micro-architecture of the design
Implement designs using low-power RTL coding techniques
Collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug
Work with the physical design team in aiding the implementation of the functional blocks
Interact with the project lead to scope tasks
Work with multiple design centers and design groups on the development of the projects
Support the post silicon team to bring up silicon in the lab
Work with the software team and in some cases the customer to ensure product meets customer use cases
Independently analyze and optimize small sub-circuit blocks within our overall design across Process, Voltage, Temperature
Requirements
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience
OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience
Prior experience with at least one major sub-circuit block from architecture definition to fine tuning
Experience Identifying and proposing innovative solutions to enhance the design of at least one major sub-circuit block
Participation in root cause investigation and silicon validation of model to hardware correlation issues
Experience Mentoring and coaching new and/or less experienced team members
Familiar with the full ASIC Design Flow, Front End, and Back End
Requires expertise in one or more of the following: Clocking and Reset, Architecture, CDC, RDC and related tools, Equivalence checking and related EDA tools, Static timing analysis and related EDA tools, Verilog coding, Design for Testability, Lab debugging and designing circuit for lab debug, Waveform debugging, EDA tools for Synthesis, Floorplanning, Physical design