Partner closely with circuit designers to plan and implement full‑custom analog/mixed‑signal layouts for blocks such as PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and high‑speed I/O.
Build optimized floorplans and routing that balance area, parasitics, matching, and congestion for both block‑level IP and top‑level SoC integration.
Apply best‑practice layout techniques to meet stringent matching, noise, and accuracy specs.
Optimize for parasitic R/C, coupling, IR drop, and electromigration to achieve noise, timing, and power targets.
Run and debug DRC, LVS, ERC, DFM, and antenna checks, driving all violations to closure.
Support post‑layout extraction and simulation, iterating layout with circuit designers until full spec closure.

An experienced analog/mixed‑signal IC layout engineer with 5 years experience delivered silicon in CMOS/FinFET nodes.
Deep proficiency in Cadence Virtuoso (XL/GXL) or equivalent custom layout environments, including constraint‑driven layout and PCells.
Strong understanding of CMOS devices, interconnect stacks, and advanced‑node rules, including multi‑patterning, density/fill, and lithography‑driven constraints.
Fluent in physical verification flows (Calibre, PVS, Assura, etc.) for DRC, LVS, ERC, LPE/RC, DFM, and antenna checks.
Detail‑oriented and organized, able to own complex blocks independently while communicating effectively with distributed design teams.
Bonus points if you bring experience in advanced FinFET nodes (7/5/3 nm), high‑speed / RF‑adjacent circuits (SerDes, CDR, LNAs, VCOs, RF front‑ends), and scripting (SKILL, Python, Tcl/Perl) to automate layout and verification.

Mixed Signal IC Layout Design Engineer – Contractor

Key skills