Lead small project teams of design and simulation engineers to deliver innovative high quality packaging solutions
Interface with package suppliers to select package technology to ensure manufacturability, and compliance with performance, reliability, and cost requirements

Experience in substrate and/or board design for package technologies
Proven ability to lead complex projects involving cross-functional stakeholders
Basic usage of tools and workflows in Cadence Allegro (3DIC/ISP/APD/SiP)
Bachelor’s degree in electrical engineering or related fields and 5+ years of related professional experience
Master’s or PhD degree with IC / Packaging focus preferred
Experience with current generation HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIE, Ethernet, etc
Good understanding of signal and power integrity at substrates, board, package, and system level
Understanding of advanced 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB, (c) CPO, (d) CPC
Familiarity in tools and workflows: Cadence Sigrity/Clarity/Innovus/Virtuoso, Ansys, AutoCAD, SolidWorks
Experience contributing to tool, process, and flow development, library maintenance
Experience interacting with chip design and electrical simulation teams to optimize the design
Familiarity with running and interpreting signal and power simulations is a plus
Ability to manage programs involving cross-functional teams

Advanced Packaging Design Engineer

Key skills