Staff Engineer, Digital Design Engineering

Role Overview

• Supporting feasibility and definition of product requirements of high-speed data communication products
• RTL design of owned blocks using SystemVerilog
• Creating/managing verification plans by understanding the top-level design and working with other design engineers
• Block and top-level RTL and gate level verification and regressions using SystemVerilog
• Supporting Synthesis, STA, DFT and Place and Route supervision
• Bench validation of owned functions
• Working with test engineers in helping them finalizing their test programs towards product introduction
• Answering customer & apps questions as needed

Requirements

• MSEE with specialization in IC Design (VLSI)
• At least 8+ years of experience in digital design
• High speed and low power RTL Design and Verification using Hardware Description Languages (preferably System Verilog)
• Hands-on experience in digital design & verification tools and methodologies
• Experience in synthesis, DFT and supervision of timing driven Place and Route
• UVM Verification background and experience in Video/Audio communication and processing is a plus

Benefits

• Beneficial programs
• Continuous learning opportunities