About this role
Role Overview
- Contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives
- Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces
- Using thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests
- Debugging RTL and Gate simulations and work with design engineers to verify fixes
- Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC
- Replicating silicon bugs in simulation environments and validating fixes or SW workarounds
- Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up
- Evaluating latest verification methodologies and developing scripts etc. to automate verification flows
Requirements
- Bachelors in Engineering and 12+ years of related experience; or Masters degree in Engineering and 10+ years of related experience; or PhD in Engineering and 7+ years of related experience
- MS or PhD is preferred
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time