lead micro-architecture and RTL development and HW/SW co-design efforts
define ASIC and/or block architecture, micro-architecture and register specification
conduct detailed architectural and/or design requirement reviews with customers, cross-functional teams, IP Vendors
implement a specification using RTL coding techniques and best practices
work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff
work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation, performance analysis and debug
help develop and/or evaluate design and verification methodologies and participate in improving existing ones
provide mentorship to the more junior team members

Bachelor’s degree in Computer Science, Electrical Engineering or related fields
12+ years of related professional experience
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience
Creating architectural, micro-architectural and Register specifications
Verilog/System Verilog RTL coding with System Verilog Assertions
Well versed in all stages of the ASIC design flow (including specification, architecture, and design implementation)
Expertise in any of the following domains: Computer Architecture, Embedded Systems Architecture, Networking, Machine Learning Accelerators
Experience with scripting in Perl/Python/Shell

Principal ASIC Design Engineer

Key skills