Principal Engineer, Mixed-Signal Design Engineering

Role Overview

• Lead architect for clock generation and distribution in an advanced mixed-signal IC for pin electronic testing
• PLL design, integration and debug
• Multi-GHz clock distribution
• Multi-chip synchronization
• Phase interpolators
• Circuits for measuring and correcting timing errors
• Assist in architecture development of a receive path which include subblock specifications which may include CTLE, PGA and A/D converter

Requirements

• PhD required
• 5-10 years of experience in analog design and design integration
• Analog/RF Designer experienced in CMOS IC design with multiple tapeouts
• Good understanding of Analog/RF circuits, and systems
• Communication theory with a particular emphasis on equalization of a wired link
• MOS device modeling and operation
• Signal integrity
• SerDes
• Extensive experience in PCB design, troubleshooting and RF measurements

Benefits

• medical, vision and dental coverage
• 401k
• paid vacation
• holidays
• sick time
• discretionary performance-based bonus