Design and support DRAM interface logic implementation
Ensure quality design through detailed design analysis using leading edge tools
Lead the extended team to support simulation, synthesis, formal verification, constraint definition, and validation of design
Collaborate with Internal and External teams to enable customer success
Refine solution by consulting with layout engineers to optimize area and performance
Define DRAM system timing budget goals aligned to product requirements
Generate collateral to support an IP release including design specifications
Requirements
Strong understanding and experience with high performance DRAM interface design
Experience with SOC architecture and how the memory interface fits into system
Excellent communication and cross-functional collaboration skills + usage of cloud based documentation
Ability to analyze complex trade-offs and make data-driven decisions
Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog
Strong understanding of physical implementation and timing closure with process variation
Understand Signal Integrity and related design impacts
Must have legal authorization to work in the US.
Bachelors in Engineering (EE, CE, or CS preferred) and 12+ years of related experience; OR Masters degree in Engineering and 10+ years of related experience.