Work on verification of Marvell's AI/ML, Network processing, Compute, Automotive, and Baseband SoCs and IPs
Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology
Develop verification testplan and write tests using random techniques and coverage analysis
Work with designers to ensure the verification is complete
Develop tests and tune the environment to achieve coverage goals
Debug failures and work with designers to resolve issues
Architect, develop and maintain tools to streamline the design of state-of-the-art multicore SoCs
Experience with analysis/closure of code and functional coverage

Strong experience developing complex/random verification environments using System Verilog/UVM
Strong experience with writing and executing detailed verification test-plan
Strong experience with scripting languages such as Python or Perl and EDA verification tools
Strong experience with object-oriented design and implementation
Hands-on verification experience with subsystems such as ARM/processor, memory, networking, NoC, and Cache designs (preferred)
Experience with protocols such as AMBA, PCIe, Ethernet, I2C, SPI, and UART (preferred)
Working knowledge of C/C++ for modeling and code development (preferred)
Familiarity with Post-Silicon validation and debug (preferred)
Experience with Gate Level Simulations (preferred)
Excellent communication skills to interface internally and externally

Principal Design Verification Engineer

Key skills