Lead the development of complex SubSystem emulation models, including design integration, environment setup, compilation, and debug across industry-leading platforms (e.g., Veloce, ZeBu, Palladium)
Drive emulation bring-up activities, including clock/reset sequencing, firmware boot, and system validation using pre-silicon hardware models
Create and execute emulation test plans to support verification, performance analysis, software development, and system validation needs across multiple teams
Collaborate closely with RTL design, verification, and firmware teams to define requirements, develop accurate hardware models, and ensure seamless integration into the emulation environment
Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions
Optimize emulation performance, including model partitioning, timing, and runtime efficiency
Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell) and tooling enhancements
Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool capabilities, resolve technical issues, and drive feature improvements

BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience)
Experience with System Verilog, UVM
Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment
Experience with scripting language such as Python or Perl and EDA Verification tools
Experience with Object-Oriented Design and implementation
Good understanding of Linux O.S
Good programming skills desired, especially C++ and ARM assembly
Understanding of networking protocols, a plus

Principal Emulation Engineer

Key skills