Work in a team environment to create and engineer digital design subsystems from concept through to tape-out
Convert subsystems into final designs for integration into the final product
Support post-silicon activities including validation, characterization, and product test
Design and develop a variety of digital and DSP IP blocks

Must be graduating May/June 2026 with a Masters or PhD in Electrical Engineering with coursework in analog/mixed signal integrated circuit design
Knowledge of Verilog RTL language
Understanding of the digital design flow from architecture, RTL design, clock domain/reset domain crossing, verification, timing constraints, and synthesis
Experience designing and verifying complex state-machines
Organized and detailed with strong communication skills
Possess outstanding analytical and problem-solving skills
Results-oriented and thrive in a dynamic environment

Entry Level Analog Design Engineer – GV

Key skills