SoC Logic Design Engineer

Role Overview

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design
• Participates in the definition of architecture and microarchitecture features of the block being designed
• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence
• Applies various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals
• Works with IP providers to integrate and validate IPs at the SoC level

Requirements

• Bachelor's degree in Electrical/Computer Engineering or related STEM field with 6 years or more relevant experience
• Master's degree in Electrical/Computer Engineering or related STEM field with 5 years or more relevant experience
• SOC or Subsystem RTL design and integration using Verilog/SystemVerilog
• IP RTL design using Verilog/SystemVerilog
• Experience with SoC flows for Reset, Power Management, Interrupts and Error Handling

Benefits

• Competitive pay
• Stock bonuses
• Health insurance
• Retirement plans
• Vacation