Define top-level or cross-subsystem digital architecture for Satellite communication ASICs and SoCs.
Lead hardware realization of key communication functions such as modem pipelines, coding engines, digital beamforming, switching fabrics, and packet/data processing.
Drive end-to-end technical planning from concept through silicon validation.
Establish system-level tradeoffs among throughput, latency, power, die area, reliability, and manufacturability.
Provide technical leadership across design, verification, physical design, firmware, packaging, and system teams.
Review and influence architectural partitioning between ASIC, FPGA, software, and RF/analog domains.
Develop methodologies and reusable IP strategies that improve schedule, quality, and scalability.
Mentor technical leaders and act as a go-to expert for critical design reviews and issue resolution.
Support roadmap planning and future product definition.

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
12+ years of ASIC design experience, including ownership of complex chips or multiple tape-outs.
Expert-level knowledge of digital design, microarchitecture, and full-chip tradeoffs.
Proven success leading technically exciting silicon programs.
Strong understanding of communication signal-processing hardware and system integration.
Ability to influence across organizations and communicate complex technical topics clearly.

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Bonuses based on the company's intent to reward individual contributions

Principal ASIC Design Engineer

Key skills