Architect and implement simulation test bench in UVM
Develop and execute test-plans for verifying correctness and performance of the design
Own and debug failures in simulation to root-cause problems
Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations

Bachelor’s degree in CS/EE with 13+ years of relevant experience, or Master’s degree in CS/EE with 11+ years of relevant experience
Strong background in IP verification, including methodology and testbench development
Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++
Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations
Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus
Strong analytical and problem-solving skills
Ability to manage multiple tasks in a fast-paced environment
Excellent communication, interpersonal, and teamwork skills
Capable of interfacing effectively at all levels within and outside the organization
Proactive in participating in problem-solving and quality improvement initiatives
Experience in working on processor-based subsystems
Experience in working on HW Security is desirable

competitive compensation
great benefits
workstyle within an environment of shared collaboration, transparency, and inclusivity
tools and resources for success and development

Principal Engineer, Design Verification

Key skills