Senior Testchip SoC Physical Design Engineer, Integration & Methodology

Role Overview

• Develop layout design methodology for testchip development in next generation process nodes
• Work closely with Process Integration, Yield and QnR to define critical Design features for early tests
• Establish and maintain hierarchical layout design specifications for integration
• Build and execute tactical plans for hierarchical SOC layout design
• Drive all aspects of physical design convergence

Requirements

• Master's degree in electrical engineering or related field
• Minimum of 5 years of experience in physical/layout design in advanced technology nodes
• Proficiency in Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
• Knowledge of design rules and layout constraints in advanced semiconductor processes
• Experience with floorplanning, hierarchical design integration, and layout verification/debug

Benefits

• Health insurance
• Retirement plans
• Paid time off
• Flexible work arrangements
• Professional development
• Stock bonuses