Develop and execute sophisticated verification plans to validate CPU logic
Create scalable, reusable verification environments using UVM-based testbenches
Perform in-depth functional coverage analysis
Execute complex system-level simulations to validate functionality, power consumption, and timing characteristics
Debug and perform root-cause analysis of issues in pre-silicon environments
Develop automation scripts and tools using Python, Perl, C++, or similar languages
Partner closely with CPU architects, RTL developers, and physical design teams
Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related STEM field with 1+ years of relevant experience OR a PhD in the same field
1+ years of experience in hardware modeling languages such as Verilog, VHDL, or SystemVerilog
Experience developing UVM-based testbenches for reusable and scalable verification environments
Programming skills in at least one language such as Python, Perl, or C++
Computer architecture fundamentals, with emphasis on CPU microarchitecture
Experience in debugging and validation, including functional coverage analysis, test development, and root cause analysis