Develop and execute comprehensive IP verification plans to ensure compliance with microarchitecture specifications
Design, implement, and maintain test benches and verification environments to achieve optimal coverage
Define and run system simulation models to verify IP design functionality, analyze power and timing, and identify bugs
Debug, root cause, and resolve pre-silicon design issues, implementing corrective measures for test failures
Collaborate with architects, RTL developers, and physical design teams to enhance the verification process for complex designs
Document verification plans and present technical reviews to design and architecture teams
Maintain and improve functional verification infrastructure, methodologies, and related workflows
Contribute to the definition and refinement of verification infrastructure and test framework methodologies (TFMs)

Bachelor's degree in electrical engineering, Computer Engineering or computer science or a related technical discipline
6 or more years of relevant experience; or master's degree with 4 or more years of experience; or PhD with 2 or more years of experience
3+ years with proficiency in System Verilog with a strong understanding of OVM and UVM methodologies
Experience in functional verification of IP designs, including debugging and root cause analysis
Hands-on expertise with digital design fundamentals, hardware simulation, and verification tools
Demonstrated experience in developing test content, validation tools, and methodologies
Solid knowledge of microarchitecture, hardware design, and power/performance validation

Design Verification Engineer

About this role