Lead the design and delivery of complex ASIC IP or subsystems from specification through RTL release.
Define microarchitecture for high-speed, power-efficient digital signal-processing and control logic.
Drive IP or subsystem trade studies involving throughput, latency, area, power, reliability, and schedule.
Collaborate with systems, algorithm, and architecture teams to translate communication requirements into hardware implementations.
Partner with verification, DFT, physical design, and firmware teams to ensure successful integration and tape-out readiness.
Review RTL, test plans, and implementation results to maintain high design quality.
Identify and mitigate technical risks early in the development cycle.
Mentor junior engineers and help establish standard processes in coding, review, and debug.
Support post-silicon bring-up and root-cause analysis of lab or field issues.
Requirements
BS or MS in Electrical Engineering, Computer Engineering, or related field.
5–8+ years of ASIC digital design experience.
Proven experience owning large blocks or subsystems in ASIC or FPGA development.
Strong expertise in System Verilog/Verilog RTL design and debug.
Working knowledge of synthesis, STA concepts, CDC/RDC, and integration flows.
Experience balancing PPA tradeoffs in production-quality designs.
Demonstrated ability to work across multidisciplinary teams.
Benefits
Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.