Define microarchitecture and implement RTL for SoC blocks
Collaborate with IP providers to integrate IPs into the SoC
Collaborate with verification and firmware teams to meet functional and performance goals
Own design quality including clock/reset/power domain crossings and timing constraints
Collaborate with physical design teams to meet timing/area/power goals
Requirements
7+ years of experience with a Bachelor's degree, 5+ years with a Master's degree, or 3+ years with a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
RTL design, coding, and simulation using SystemVerilog
Microarchitecture and SoC architecture
System-level design principles like power, performance, and area trade-offs/optimizations.
Proven ability to effectively communicate across multidisciplinary teams