Define, develop, debug and improve new innovative Design verification environments
Relevant and hands-on experience with development of test benches, verification plans, test-plans and coverage definitions for complex IPs, Sub-systems and SoCs
Interacting with architecture, FW and design teams to debug and resolve critical issues
Requirements
B.S. in electrical engineering, computer science or equivalent with extensive industry experience
6-8 years of deep verification exposure
Experience with RTL debugging, score boarding and code coverage analysis
Proven expertise with writing and tracking detailed test-plans at all levels.
Hands-on experience with DDR, PCIe/NVMe or NAND interfaces is an advantage
Expert level with System-Verilog and UVM methodologies
Familiarity with C is an advantage
Exposure to gen-AI tools (Claude-Code, others) is an advantage