Support development and maintenance of assembly design rules that address capabilities and constraints of advanced silicon packaging and heterogeneous integration.
Contribute to package assembly design kit by creating and evaluating test cases for different assembly configurations.
Evaluate constraints arising from multidie integration, ensuring compliance with documented assembly rules.
Interpret design rule impacts on manufacturability, yield, and system-level integration requirements.
Assist in reviewing bump layouts and propose corrections across a design life cycle.
Prepare reports summarizing rule checks, violations, and recommendations.

Currently pursuing a Masters or PhD in Electrical Engineering, Computer Engineering, or a related field with a focus on semiconductor devices or silicon testing.
3+ months experience with packaging assembly design.
Experience with root cause analysis and problem-solving in a technical environment.
Familiarity with technical documentation and communication of engineering results.
Demonstrated ability to collaborate effectively with cross-functional teams in a research or engineering environment.
Knowledge of design for debug (DFD) principles and their applications in silicon validation.
Strong interest in continuous learning and improvement within the semiconductor domain.
Passion for making meaningful contributions to innovative technologies and products.

Product Engineering Graduate Intern

Key skills