About this role

Take technical ownership of the complete tape-out flow
Drive EIC+PIC DfX co-integration across a 300 mm graphene photonics platform
Own the complete tape-out flow including Mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign-off, and rule file maintenance
Lead GDS and reticle-to-fab delivery, ensuring compliance with fab specifications
Drive DFM and DFT integration through yield optimization, hotspot mitigation, layout optimization
Design and integrate special GDS structures
Act as the primary interface between mask shops, foundry lithography/metrology teams, EDA vendors, and cross-functional teams
Maintain GDS version control and audit-trail archiving while supporting first-silicon debug

MS or PhD in Electrical Engineering, Physics, or a related field
5+ years of experience in semiconductor or photonics tape-out, layout integration, and Mask Data Preparation (MDP)
Strong expertise in GDSII/OASIS, DRC/LVS/ERC verification flows, and industry-standard tools such as Calibre and Synopsys ICV
Hands-on experience with production tape-out flows including DFM, DFT, ESD, seal ring/kerf, and RDL layout implementation
Familiarity with OPC flows for advanced photonics or CMOS nodes
Experience coordinating with mask shops and foundry partners
Experience with Photonic IC technologies (Si, SiN, etc.) or photonic/electronic co-design EDA tools such as Cadence EPIC or Lumerical is considered a plus
Background in mask shops or EDA software environments is highly desirable

Electronic-Photonics IC Mask Data Preparation, GDS Data Integration Engineer

Key skills