Mixed Signal Design Verification Engineer

Role Overview

• Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements
• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications
• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs
• Replicates, root causes, and debugs issues in the presilicon environment
• Finds and implements corrective measures to resolve failing tests
• Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
• Maintains and improves existing functional verification infrastructure and methodology

Requirements

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience
• OR
• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience
• Experience in Digital logic experience
• Experience in VHDL/Verilog/System Verilog
• Experience in Testbench component development (preferably in OVM/UVM), and design debugging skills

Benefits

• competitive pay
• stock bonuses
• benefit programs which include health, retirement, and vacation