Architecting the clock domain to satisfy functional, physical and testing design requirements.
Engage with multiple teams and design the GPU or CPU clocks.
Improve Power, Performance, and Area (PPA) of NVIDIA chips by evaluating trade-offs.
Collaborate with Physical design and timing team to evaluate Clocking concerns.
Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch.

Bachelor's degree or higher in Electrical Engineering (or equivalent experience).
Understanding of logic optimization techniques and PPA trade-offs.
Shown ability to collaborate with multiple teams.
Experience in RTL design (Verilog), verification and logic synthesis.
Strong coding skills in Python or other industry-standard scripting languages.

ASIC Clocks Design Engineer – New College Grad

Key skills