About this role

Develop functional verification plans and test benches based on microarchitecture specifications.
Design and maintain verification environments that ensure comprehensive coverage and robust testing of IP logic.
Execute verification plans and perform system simulations to confirm compliance with specifications, analyze power and timing, and identify bugs.
Debug issues in the pre-silicon environment, identify root causes, and implement corrective measures to address failing tests.
Collaborate with architects, RTL designers, and physical design teams to verify complex architectural and microarchitectural features.
Document test plans, participate in technical reviews, and drive improvements to verification strategies and infrastructure.
Maintain and enhance existing functional verification methodologies and frameworks.
Contribute to the definition and optimization of new verification infrastructure and related tools and flows.

Bachelor’s in electrical engineering or computer engineering or computer science
1+ years of experience in IP design verification or a related domain
Must have the anticipated degree or expect to have the anticipated degree by July 2026
6+ months of experience with debugging techniques and tools
Knowledge of RTL design concepts and methodologies
Familiarity with design for verification (DFV) principles and practices
Understanding of developing and maintaining IP test environments.

IP Design Verification Engineer

About this role