Researching and defining the SW solutions based on the PCIe standard and the Linux implementation for the PCIe stack
Designing and Implementing the SW Stack for the communication between the EyeQ SoCs laying the infrastructure for cross chip neural networks.
Defining the future HW solutions by working closely with the SoC Architecture team in a SW/HW co-development environment.
Performing performance analysis, feasibility studies, PoCs and optimization flows to achieve the highest performance with minimal resources.
Work closely with the Linux Kernel team and provide the technical guidance and mentoring for development engineers.

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
Very strong experience in the Linux Kernel architecture, OS Internals and subsystems (Memory Management, IO, Storage, Networking)
Deep understanding of PCIe standard, topologies and it’s applications.
Very good understanding of HW architecture and high bandwidth applications.
Strong experience in Performance Analysis and Debugging techniques.
Experience with HW architectures (MIPS & RISCV) and their implementation in the operating system is a big advantage.
Experience in the user space is a good advantage.

Embedded Linux OS Architect

Key skills