About this role
Role Overview
- Design and develop SoC-level and HBM-cube-level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes.
- Perform EM/IR analysis and optimization using industry-standard tools (e.g., Cadence RedHawk, Ansys Totem) to ensure power integrity across dynamic workloads.
- Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation.
- Drive power integrity closure across multi-mode/multi-corner scenarios, identifying and mitigating droop, noise, and electromigration risks.
- Work with package and system teams to co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution.
- Develop and validate power models, including activity-based current profiles and transient analysis for realistic workload scenarios.
- Partner with architecture and design teams to influence power-aware design decisions, including power domains, gating strategies, and current demand shaping.
- Support signoff activities, including EM, IR, and reliability verification, ensuring design meets long-term reliability and manufacturability goals.
- Debug and root-cause PDN-related issues during pre-silicon and post-silicon phases, including silicon correlation and model refinement.
- Improve PDN methodologies through automation, scripting, and best-practice development across HBM programs.
Requirements
- Strong experience in power delivery network design and analysis for complex SoCs or high-performance ASICs.
- Proficiency with EM/IR analysis tools such as RedHawk, Totem, or equivalent.
- Proficiency with Spice based simulation tools and 3D modeling of PDN networks.
- Solid understanding of IR drop, electromigration, dynamic voltage droop, and power noise mechanisms.
- Experience with physical design flows and close interaction with floorplanning, routing, and implementation teams.
- Familiarity with full RTL-to-GDSII design flow and signoff methodologies.
- Strong analytical and debugging skills with the ability to drive complex issues to closure.
- Experience with HBM, DRAM, or memory-centric SoC designs.
- Familiarity with die-package-system co-design and advanced packaging technologies (2.5D/3D integration).
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 10 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
Benefits
- health insurance
- dental and vision plans
- income protection programs
- paid family leave
- robust paid time-off program
- paid holidays