Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement
Memory bit-cell and complex periphery IC layout and automation
Memory array/IP design, memory circuit innovation, test-chip design
Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment
Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM
Design trade-offs between power, performance, and area (PPA)
Custom digital circuit design, simulation, layout design, and verification
Knowledge of EDA tools used for custom digital and memory circuit design

Memory Circuit Design Engineer

About this role