Principal AI Forward Deployment Engineer

Role Overview

• Customer-Embedded Deployment. Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows
• from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging.
• Applied AI for Chip Design. Architect and tune agentic workflows, prompt strategies, RAG pipelines, and tool-calling patterns on top of flagship LLMs (Claude, GPT, Gemini, Llama, Qwen, etc.) to automate real EDA tasks
• debug triage, constraint authoring, ECO loops, PD recipe tuning, methodology Q&A, log/report summarization, and design-review copilots.
• Methodology & Flow Integration. Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term.
• Productivity & ROI Ownership. Define and report KPIs
• cycle-time reduction, engineer-hours saved, iteration count, first-pass success, license/compute efficiency. Own the story from pilot to production rollout across BUs and sites.
• Trusted Technical Advisor. Be the senior technical face to customer fellows, methodology leads, and design-team principals. Run design reviews, technical readouts, and joint roadmaps. Translate customer pain into actionable feedback for Cadence R&D and AI platform teams.
• AI Systems Enablement (plus). Where needed, guide customer IT/InfoSec on secure LLM access patterns, on-prem vs. gateway deployment, model routing, prompt/response logging, data-egress controls, and GPU/inference capacity planning.
• Knowledge Multiplier. Capture playbooks, reference designs, and 'golden prompts' so every deployment compounds. Mentor field AEs, FAEs, and customer champions.

Requirements

• BS/MS/PhD in EE, ECE, CS, or related discipline
• 10+ years of hands-on semiconductor / chip design experience in one or more of: front-end design (RTL, micro-architecture, DV), physical design / implementation (synthesis, P&R, timing, power, signoff), CAD / methodology / flow development, or design execution / project technical leadership on production tape-outs
• Deep, practitioner-level fluency with industry EDA flows and pain points
• you have personally shipped silicon and know where the cycle-time and engineer-time really go
• Demonstrated ability to apply LLMs / AI tools to get real engineering work done (e.g., agent-based debug, code/RTL generation assist, scripted automation, copilots, RAG over design docs/logs)
• Excellent customer-facing communication: equally credible with a staff RTL engineer, a PD methodology lead, and a CAD / design-enablement leader
• Bias to action, ownership, and shipping
• Comfortable being the single throat-to-choke for a customer-facing AI deployment.

Benefits

• Health insurance
• 401(k) matching
• Paid time off
• Professional development opportunities
• Flexible working hours