Design complex layouts of analog signal circuits based on detailed design specifications.
Conduct a comprehensive set of design verification checks, including process design rules, electron migration, voltage drop (IR), ESD, and other reliability assessments.
Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet performance and electrical requirements.
Perform floor planning and detailed signal planning for complex analog circuits, ensuring optimization for area, power, reliability, and performance.
Drive the development and implementation of innovative analog layout methodologies to improve productivity and layout quality.
Troubleshoot issues related to design, tools, flows, and methodologies utilized in analog layout design.
Collaborate closely with cross-disciplinary teams to meet design specifications, align on requirements, and negotiate layout tradeoffs.
Requirements
Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience
Or a Master’s degree in the same field with 2+ years experience
Analog device and metal layout fundamentals, including analog/mixed-signal fundamentals
Cadence Virtuoso Layout Suite and Calibre/ ICV DRC for design and verification tasks
CMOS technologies and high-voltage rules
Floor planning and hierarchical layout planning for analog and mixed-signal blocks
Conducting performance verification for layouts and debug layout-related issues