Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams
play a key role in full chip design integration with the testability features coordinated in the RTL
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows
Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies

Bachelor's or a Master's Degree in Electrical or Computer Engineering required
at least 7 years of experience
Prior experience working in the latest innovative trends in DFT, test and silicon engineering
Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Prior experience working with Gate level simulation, debugging with VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE patterns, P1687

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units which vest after defined periods of time
10 paid holidays per full calendar year plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
non-exempt employees receive 16 days of paid vacation time per full calendar year
exempt employees participate in Cisco’s flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
optional 10 paid days per full calendar year to volunteer
for non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies

ASIC DFT Engineer

Key skills