Responsible for the micro-architecture and design of the AI Control sub-system modules including Hardware Execution Engines.
Own design, document, execute and deliver fully verified, high performance, area, and power efficient RTL to achieve the design targets and specifications
Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies
Design and Implement logic functions that enable efficient test and debug
Participate in silicon bring-up and validation for blocks owned

Bachelor’s degree in electrical engineering, Computer Engineering or Computer Science with 5 years of meaningful work experience
Experience in micro-architecture and RTL development (Verilog/System Verilog), focused on Processor and sub-system design, Digital Signal Processing blocks is a plus
Exposure to Computer Architecture & Arithmetic is required. Experience with RISC-V/Tensilica/ARM/Mips processors is required
Exposure to Computer Architecture & Arithmetic is required. Experience with Floating point and Integer Arithmetic and Numerics is a plus. Exposure to Interconnect and Bus Interfaces is required.
Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
Strong interpersonal skills and an excellent teammate.

Design Engineer

Key skills