Experienced Staff Design Engineer, Verification

Role Overview

• Perform various tasks associated with Design Verification RISCV architecture Processors/Cores.
• Reviewing Design and RISCV Standard Specifications.
• Test Bench Development.
• Test Plan Creation.
• Tests Creation.
• Test Case Debug.
• Coverage Closure.
• Modeling, Flow and Methodology development.

Requirements

• Graduates in Electrical, Electronics and/or Computer Engineering major or a related field with Computer architecture and VLSI Design as an important and primary part of the curriculum.
• Must have at least an overall 3.0 GPA.
• Bachelor’s, with 3 to 5 years of experience or Master’s degree holders with 1 to 3 years of experience.
• Experience should be relevant/recent and appropriate.
• Candidate should possess a good understanding of Hardware Description Languages such as Verilog/System-Verilog.
• Candidate should have good background/knowledge of typical IP Development/Verification and/or SOC Development/Verification process.
• Must have knowledge in UNIX OS, Assembly & C Programming.
• Python or Perl Scripting language.

Tech Stack

• Assembly
• Perl
• Python
• Unix