CPU-SoC Silicon Design Engineering Intern

Role Overview

• Involving in the training, design and development of next generation SOC/CPU for wide range of Intel products and Internet of Things
• Assist design unit owner in Register Transfer Level RTL model functional validation
• Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions
• Verify the circuit behavior against the original simulation model and first silicon
• Define VLSI Structural Design methodology and developing design flows
• Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration
• Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power
• Responsible for Integration of Third party IPs -
• Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company
• Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices
• System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android and Windows-based tablets and phones
• Responsible to validate and integrate third party IPs ensuring they meet product specification and functionality before they are productized into physical chip
• Required to work very closely with design teams and architects to implement the low-level RTL design to ensure overall good functionality of the chip
• Develop specific test environment/platform, validation methodology and test plan to validate SOC design by identifying and exercising boundary conditions and special cases in an effort to break the chip to find that last elusive bug
• Oversees definition, design, verification, and documentation for SoC System on a Chip development
• Determines architecture design, logic design, and system simulation
• Defines module interfaces/formats for simulation
• Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
• Contributes to the development of multidimensional designs involving the layout of complex integrated circuits
• Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
• Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results

Requirements

• Students pursuing a Bachelor degree in EECS or related major with good CGPA
• Good communication skills and proficient in English
• Knowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog is major plus

Tech Stack

• Android
• IoT
• Unix

Benefits

• Flexible work arrangements
• Professional development